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[VHDL-FPGA-Verilog] UP3_RTC_CLOCK

Description: 在UP3开发板上已经验证过的VHDL代码。精确到十分之一秒，具有闹钟，整点报时，时间可重新设置等功能，在LCD1602上显示。绝对推荐，比网上其他类似代码功能要全而且经过验证。最关键的是该代码是直接通过I2C总线来获取UP3开发板上的实时时钟芯片的时间的,当然也可以通过I2C对时钟芯片进行设置.-In the UP3 development board has been verified VHDL code. Accurate to one-tenth of seconds, with the alarm clock, the whole point timekeeping, time and other functions can be re-instated in the LCD1602 display. Absolutely recommended online than other similar features to the entire code and verified. Most crucial point is that the code is directly through the I2C bus to obtain the UP3 development board real time clock chip time, of course, can also I2C clock chip on the set.
Platform: | Size: 1367040 | Author: kehan | Hits:

[VHDL-FPGA-Verilog] scaler

Description: VHDL描述的简易图像缩小模块，将PAL制720×576的图片缩小为512×410，采用最近临域法，13.5MHz时钟下可实时处理PAL视频。-VHDL description of a simple image to narrow the module, will be PAL system of 720 × 576 image reduced to 512 × 410, using the recent Pro-domain method, 13.5MHz clock can handle PAL video in real time.
Platform: | Size: 9216 | Author: wgy | Hits:

[VHDL-FPGA-Verilog] DS1307_LCD

Description: 通过IIC总线读写实时时钟DS1307，并把时、分、秒显示在12864液晶屏上，用的CycloneII EP2C8，Quartus环境-Through the IIC bus read and write real-time clock, DS1307, and the hours, minutes and seconds displayed on the LCD screen on the 12864, used CycloneII EP2C8, Quartus environment
Platform: | Size: 1311744 | Author: iversn | Hits:

[VHDL-FPGA-Verilog] clock

Description: 用VHDL语言写的实时时钟 用数码管显示 基于的控制芯片是EP1C6Q24C08-VHDL language used to write the real-time clock with digital display are based on the control chip EP1C6Q24C08
Platform: | Size: 353280 | Author: 周到 | Hits:

[Embeded-SCM Develop] serial

Description: -- 本模块的功能是验证实现和PC机进行基本的串口通信的功能。需要在 --PC机上安装一个串口调试工具来验证程序的功能。 -- 程序实现了一个收发一帧10个bit（即无奇偶校验位）的串口控 --制器，10个bit是1位起始位，8个数据位，1个结束 --位。串口的波特律由程序中定义的div_par参数决定，更改该参数可以实 --现相应的波特率。程序当前设定的div_par 的值是0x104，对应的波特率是 --9600。用一个8倍波特率的时钟将发送或接受每一位bit的周期时间 --划分为8个时隙以使通信同步. --程序的工作过程是：串口处于全双工工作状态，按动SW0，CPLD向PC发送“welcome" --字符串（串口调试工具设成按ASCII码接受方式）；PC可随时向CPLD发送0-F的十六进制 --数据，CPLD接受后显示在7段数码管上。-- The module s function is to verify the implementation and the basic PC-to serial communication functions. Required at - PC machine on the installation of a serial debugging tools to verify the function of the procedure. - Implementation of a program to send and receive a 10 bit (that is, no parity bit) Serial Control - System, and 10 bit is a start bit, 8 data bits, 1 Ending - Bit. Serial Porter law procedures defined by the parameters div_par decision to change the parameters can be real - Is the corresponding baud rate. Procedures set div_par the current value is 0x104, the corresponding baud rate are - 9600. 8 times the baud rate with a clock will be sent or received every bit of the cycle time - Is divided into eight time slots in order to enable synchronous communication. - Procedures for work processes are: full-duplex serial port in job status, rather than pressing SW0, CPLD to the PC to send "welcome" - String (serial debug tools is set to accept by way of A
Platform: | Size: 65536 | Author: johnson | Hits:

[VHDL-FPGA-Verilog] fpga.fifo

Description: 异步FIFO是用来适配不同时钟域之间的相位差和频率飘移的重要模块。本文设计的异步FIFO采用了格雷（GRAY）变换技术和双端口RAM实现了不同时钟域之间的数据无损传输。该结构利用了GRAY变换的特点，使得整个系统可靠性高和抗干扰能力强，系统可以工作在读写时钟频率漂移达到正负300PPM的恶劣环境。并且由于采用了模块化结构，使得系统具有良好的可扩充性。-Asynchronous FIFO is an important module which always used to absorb the phase and frequency offset between different clock domain in communication area .In this paper, an FIFO module is designed using Gray convert technology and dual-port ram , which realizing scatheless transmit between different clock domain. The advances of Gray (Only one bit changes between neighboring two clock ) improves the reliability and anti-jamming capability of the system. And the system can work normally in the bad condition which the phase and frequency offset target to 300PPM. It is proved by work that the FIFO module can fulfill the demands of real-time of data transmitting system, and the module is powerful enough for more data process in the future.
Platform: | Size: 81920 | Author: 雷志 | Hits:

[Windows Develop] vclock

Description: developing the real time clock using vhdl
Platform: | Size: 4096 | Author: ravi | Hits:

[Other] ds32c35

Description: ds32c35是dalas生产的实时时钟（RTC）芯片，本程序（在EP2C8Q208C8N上调试通过）在FPGA上构建I2C接口于此时钟芯片通信。可以在LED上动态实时显示时间。利用本程序也可以改编成高精度实时时间测量的程序-ds32c35 is produced by dalas real-time clock (RTC) chip, this program (in the EP2C8Q208C8N debugging via) in the FPGA built this clock chip I2C interface to communicate. LED dynamically in real-time display of time. Using this procedure can also be adapted into a high-precision real time measurement procedures
Platform: | Size: 3898368 | Author: mn | Hits:

[VHDL-FPGA-Verilog] DigitalClock

Description: 该数字钟，采用VHDL语言编写，具有即时，跑表，调时，调分，闹铃等功能，另外还可以增加一些功能，例如正点报时等-The digital clock, using VHDL language, with real-time, PaoBiao, adjustable, adjustable, alarm functions, also can add some functions, such as punctual
Platform: | Size: 1327104 | Author: fushibin | Hits:

[VHDL-FPGA-Verilog] rtc

Description: real time clock using spartan3e fpga
Platform: | Size: 787456 | Author: ravikiran | Hits:

[VHDL-FPGA-Verilog] Counter-60

Description: In this example, counter 60 is implemented as part of the real time clock time electronic clocks. Done in the platform mentor Graphics and describes in the VHDL code. This counter has a role to the front edge of every 60 clock sends a signal following the counter.
Platform: | Size: 3956736 | Author: Milos | Hits:

[Software Engineering] RTC

Description: Implementation of Real Time Clock in VHDL coding. It can be implemented in XILINX305E FPGA kit.
Platform: | Size: 1024 | Author: VINOTH R | Hits:

[VHDL-FPGA-Verilog] VHDL--PCF8563T

Description: I2C实践，-PCF8563T实时时钟vhdl语言-I2C practice,-PCF8563T real-time clock vhdl language
Platform: | Size: 797696 | Author: 刘胜毅 | Hits:

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